Superseded Standard

IEEE 1076.6-1999

IEEE Standard for VHDL Register Transfer Level Synthesis

A standard syntax and semantics for VHDL register transfer level (RTL) synthesis is defined. The subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis is defined, along with the semantics of that subset for the synthesis domain.

Sponsor Committee
C/DA - Design Automation
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Status
Superseded Standard
Superseded by
1076.6-2004
Board Approval
1999-09-16
History
ANSI Approved:
2000-03-29
Published:
2000-03-10

Working Group Details

Society
IEEE Computer Society
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Sponsor Committee
C/DA - Design Automation
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