Inactive-Withdrawn Standard

IEEE 1076.6-2004

IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

Sponsor Committee
C/DA - Design Automation
Learn More
Status
Inactive-Withdrawn Standard
PAR Approval
2003-05-15
Superseding
1076.6-1999
Board Approval
2004-05-12
History
Withdrawn:
2010-01-09
ANSI Approved:
2004-08-25
Published:
2004-10-11

Working Group Details

Society
IEEE Computer Society
Learn More
Sponsor Committee
C/DA - Design Automation
Learn More
Working Group
SI-WG - VHDL Register Transfer Level (RTL) Synthesis Working Group
IEEE Program Manager
Vanessa Lalitte
Contact
Working Group Chair
Jayaram Bhasker
No Active Projects
No Active Standards
No Superseded Standards
No Inactive-Withdrawn Standards
No Inactive-Reserved Standards
Newswire

Sign up for our monthly newsletter to learn about new developments, including resources, insights and more.