The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
- Sponsor Committee
- C/DA - Design Automation
Learn More - Status
- Superseded Standard
- Superseded by
- 1364-2001
- Board Approval
- 1995-12-12
- History
-
- ANSI Approved:
- 1996-08-01
- Published:
- 1996-10-14
Working Group Details
- Society
- IEEE Computer Society
Learn More - Sponsor Committee
- C/DA - Design Automation
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