Define structures in STIL to support usage as semiconductor simulation stimulus; including: 1) mapping signal names to equivalent design references, 2) interface between Scan and Built-In Self-Test (BIST), and the logic simulation, 3) data types to represent unresolved states in a pattern, 4) parallel or asynchronous pattern execution on different design blocks, and 5) expression-based conditional execution of pattern constructs. Define structures in STIL to support the definition of test patterns for sub-blocks of a design (i.e., embedded cores) such that these tests can be incorporated into a complete higher-level device test. Define structures in STIL to relate fail information from device testing environments back to original stimulus and design data elements.
- Sponsor Committee
- C/TT - Test Technology
Learn More - Status
- Active PAR
- PAR Approval
- 2020-12-03
- Superseding
- 1450.1-2005
Working Group Details
- Society
- IEEE Computer Society
Learn More - Sponsor Committee
- C/TT - Test Technology
Learn More - Working Group
-
STIL.1 - IEEE Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design Environments
Learn More - IEEE Program Manager
- Tom Thompson
Contact - Working Group Chair
- Gregory Maston
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