Active PAR

P1450.6.2

Standard for Memory Modeling in Core Test Language

System on Chip (SoC) test requires reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits. This standard defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an SoC. This facilitates the development and reuse of test and repair mechanisms for memories. This standard also defines constructs that represent the test structures internal to the memory core for reuse in the creation of the tests for the logic outside the memory core. Semantic rules are defined for the language to facilitate interoperability between different entities (the memory core provider, the system integrator, and the automation tool developer) involved in the creation of an SoC. The capabilities are an extension of IEEE Std 1450.6(TM)-2005. As a result of this extension, CTL's limitations of handling memories are addressed.

Sponsor Committee
C/TT - Test Technology
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Status
Active PAR
PAR Approval
2020-02-13
Superseding
1450.6.2-2014

Working Group Details

Society
IEEE Computer Society
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Sponsor Committee
C/TT - Test Technology
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Working Group
1450.6.2WG - Working Group for Core Test Language (CTL)
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IEEE Program Manager
Tom Thompson
Contact
Working Group Chair
Saman Adham
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1450.6.2-2014

IEEE Standard for Memory Modeling in Core Test Language

Reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits is required for system-on-chip (SoC) tests. This standard defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an SoC. This facilitates the development and reuse of test and repair mechanisms for memories. This standard also defines constructs that represent the test structures internal to the memory core for reuse in the creation of the tests for the logic outside the memory core. Semantic rules are defined for the language to facilitate interoperability between different entities (the memory core provider, the system integrator, and the automation tool developer) involved in the creation of an SoC. The capabilities are an extension of IEEE Std 1450.6(TM)-2005. As a result of this extension, CTL's limitations of handling memories are addressed.

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