A methodology for accessing instrumentation embedded within a semiconductor device, without defining the instruments or their features themselves, via the IEEE 1149.1(TM) test access port (TAP) and/or other signals, is described in this standard. The elements of the methodology include a hardware architecture for the on-chip network connecting the instruments to the chip pins, a hardware description language to describe this network, and a software language and protocol for communicating with the instruments via this network.
- Sponsor Committee
- C/TT - Test Technology
Learn More - Status
- Active Standard
- PAR Approval
- 2006-03-16
- Board Approval
- 2014-11-03
- History
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- Published:
- 2014-12-05
Working Group Details
- Society
- IEEE Computer Society
Learn More - Sponsor Committee
- C/TT - Test Technology
Learn More - Working Group
-
IJTAG - Internal Joint Test Action Group
Learn More - IEEE Program Manager
- Tom Thompson
Contact - Working Group Chair
- Ian Mcintosh
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