Guidance on technical protection measures to those who produce, use, process, or standardize the specifications of electronic design intellectual property (IP) are provided in this recommended practice. Distribution of IP creates a risk of unsanctioned use and dilution of the investment in its creation. The measures presented here include protection through encryption, specification, and management of use rights that have been granted by the producers of electronic designs, and methods for integrating license verification for granted rights. (The PDF of this standard is available at no cost compliments of the Accellera Systems Initiative at https://ieeexplore.ieee.org/browse/standards/get-program/page)
Working Group Details
Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP)
This standard specifies embeddable and encapsulating markup syntaxes for design intellectual property encryption and rights management, together with recommendations for integration with design specification formats described in IEEE 1800 (SystemVerilog) and IEEE 1076 (VHDL). It also recommends use models for interoperable tool and hardware flows, which will include selecting encryption and encoding algorithms and encryption key management. The recommendation includes a description of the trust model assumed in the recommended use models. This standard does not specifically include any consideration of digitally encoded entertainment media. In the context of this document, the term IP will be used to mean electronic design intellectual property. Electronic design intellectual property is a term used in the electronic design community. It refers to a reusable collection of design specifications that represent the behavior, properties, and/or representation of the design in various media. Examples of these collections include, but are not limited to, the following: A unit of electronic system design; A design verification and analysis scheme (e.g., test bench); A netlist indicating elements and the interconnection thereof to implement a function; A set of fabrication instructions; A physical layout design or chip layout; A design intent specification The term is partially derived from the common practice for the collection to be considered the intellectual property of one party. Hardware and software descriptions are encompassed by this term.
IEEE Approved Draft Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) - Corrigendum 1: Correction to Rights Digest Description
Correct an inconsistency within 7.4.3 of IEEE Std 1735-2014. The section contains a description of a rights digest followed by details on how to calculate it. The two do not match. (Note: This corrigenda was not published as a separate document, but was incorporated into IEEE Std 1735-2014)