The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.
- Sponsor Committee
- C/DA - Design Automation
Learn More - Status
- Superseded Standard
- PAR Approval
- 2014-12-10
- Superseded by
- 1800.2-2020
- Board Approval
- 2017-02-14
- History
-
- Published:
- 2017-05-26
Working Group Details
- Society
- IEEE Computer Society
Learn More - Sponsor Committee
- C/DA - Design Automation
Learn More - Working Group
-
UVM - Universal Verification Methodology Language Reference Manual
Learn More - IEEE Program Manager
- Vanessa Lalitte
Contact - Working Group Chair
- Justin Refice
No Active Projects
1800.2-2020
IEEE Standard for Universal Verification Methodology Language Reference Manual
The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)
No Superseded Standards
No Inactive-Withdrawn Standards
No Inactive-Reserved Standards