Superseded Standard

IEEE 1800.2-2017

IEEE Standard for Universal Verification Methodology Language Reference Manual

The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.

Sponsor Committee
C/DA - Design Automation
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Status
Superseded Standard
PAR Approval
2014-12-10
Superseded by
1800.2-2020
Board Approval
2017-02-14
History
Published:
2017-05-26

Working Group Details

Society
IEEE Computer Society
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Sponsor Committee
C/DA - Design Automation
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Working Group
UVM - Universal Verification Methodology Language Reference Manual
IEEE Program Manager
Vanessa Lalitte
Contact
Working Group Chair
Justin Refice
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1800.2-2020

IEEE Standard for Universal Verification Methodology Language Reference Manual

The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)

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No Superseded Standards
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No Inactive-Reserved Standards
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