The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting, (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (which comply with this standard) to report fault coverage in a uniform way. This will facilitate the generation of a uniform coverage (and hence a uniform test quality) metric for large chips (including systems-on-chips – SOCs) with different cores and modules, for which test patterns have been independently generated.
- Sponsor Committee
- C/TT - Test Technology
Learn More - Status
- Active Standard
- PAR Approval
- 2009-03-19
- Board Approval
- 2017-12-06
- History
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- Published:
- 2018-01-31
Working Group Details
- Society
- IEEE Computer Society
Learn More - Sponsor Committee
- C/TT - Test Technology
Learn More - Working Group
-
FACR 1804 - Fault Accounting and Coverage Reporting to Digital Modules (FACR)
Learn More - IEEE Program Manager
- Tom Thompson
Contact - Working Group Chair
- Rajesh Raina
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