This standard leverages existing standards-based test access mechanisms to capture and retrieve flip-flop and array/memory states. This standard defines a methodology for scan and memory/array debug data extraction for effective functional debug of System-on-Chip (SoC) and addresses other essential architectural modifications needed to support this, such as power-management changes. This standard provides a reliable and consistent methodology on trigger-based freezing of SoC scan and array states, and retrieval of those states.
- Sponsor Committee
- C/TT - Test Technology
Learn More - Status
- Active PAR
- PAR Approval
- 2020-09-24
Working Group Details
- Society
- IEEE Computer Society
Learn More - Sponsor Committee
- C/TT - Test Technology
Learn More - Working Group
-
Scan and Array Debug - Standard for System-level State Extraction for Functional Validation and Debug
Learn More - IEEE Program Manager
- Tom Thompson
Contact - Working Group Chair
- Sankaran Menon Phd
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