This standard defines technical architectures for a quantum computers based on the technological type (e.g., fault-tolerant universal quantum computing) and one or more qubit modalities (e.g., superconducting quantum processor). The defined architectures include the hardware (e.g., signal generator) and low-level software (e.g., quantum error correction) components of a quantum computer. The standard excludes any definition of a quantum circuit or algorithm.
- Sponsor Committee
- C/MSC - Microprocessor Standards Committee
Learn More - Status
- Active PAR
- PAR Approval
- 2021-11-09
Working Group Details
- Society
- IEEE Computer Society
Learn More - Sponsor Committee
- C/MSC - Microprocessor Standards Committee
Learn More - Working Group
-
QuARC/WG - Quantum Computing Architecture Working Group
Learn More - IEEE Program Manager
- Tom Thompson
Contact - Working Group Chair
- Jonathan J. Attia
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