IThe VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined in this standard. This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.
- Sponsor Committee
- C/DA - Design Automation
Learn More - Status
- Inactive-Withdrawn Standard
- Adoption of
- 1076.4-2000
- History
-
- Published:
- 2004-11-15
Working Group Details
- Society
- IEEE Computer Society
Learn More - Sponsor Committee
- C/DA - Design Automation
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