This standard provides the definition of the language syntax and semantics for the IEEE 1800(tm)-2017 Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
This standard applies to software safety during the development, procurement, maintenance, and retirement of safety-critical software; for example, software products whose failure could cause loss of life, serious harm, or have widespread negative social impact. This standard requires that software safety be considered within the context of the system safety program throughout the software lifecycle. The scope of this standard includes only the safety aspects of the software. This standard also discusses aspects of software safety related to interoperation with other systems or constituents of a system of systems.